1. Field of the Invention
This invention relates generally to low voltage differential signaling, and more particularly to a circuit that provides a stable predrive to a BiCMOS low voltage differential signaling (LVDS) output which compensates for supply voltage variations while maintaining a suitably fast signal path.
2. Description of the Prior Art
Low voltage differential signaling (LVDS) transceiver products directed to high speed LVDS repeater types and PECL/ECL to LVDS converter types are continuously being developed and improved. These transceiver products are meant to receive a differential input signal and drive a TIA/EIA-644 compliant LVDS signal. One of the most significant technical problems associated with a high speed repeater (up to 1.36 GBps) is meeting the extremely low total jitter requirements necessary for transmission of such fast signals. For this reason, the signal paths of all high speed LVDS repeaters are fully balanced differential types. High speed BiCMOS processes are uniquely suited to such circuits due to the availability of very high speed NPN transistors; and such transistors are employed liberally in the signal paths of many LVDS repeaters. NPN devices must be driven in a narrow range of input voltage values to avoid entering the cutoff or saturation regions of operation. For this reason, difficult problems often arise in the DC biasing of NPN signal paths, especially given a range of supply voltage and temperature conditions over which all parametrics are specified.
In view of the foregoing, it would be desirable to have a circuit that provides a stable predrive to a BiCMOS LVDS output which compensates for supply voltage variations while maintaining a suitably fast signal path.
The present invention is directed to a circuit that provides a stable predrive to a BiCMOS LVDS output which compensates for supply voltage variations while maintaining a suitably fast signal path.
According to one aspect of the invention, a predrive supply voltage compensation circuit comprises:
a predrive supply voltage;
a predrive input stage responsive to a first bias current and operative to process a differential input signal and generate a first differential output signal therefrom;
a first level shifter stage responsive to the first bias current and operative to level shift the first differential output signal downward to generate a second differential output signal therefrom;
a differential gain stage responsive to the first bias current and operative to process the second differential output signal to generate a third differential output signal therefrom;
a second level shifter stage connected to a pair of predrive output nodes and responsive to a second bias current to level shift the third differential output signal downward as the predrive supply voltage increases to generate a predrive output signal at the pair of predrive output nodes; and
a bias current supply circuit configured to generate the second bias current such that the second bias current is proportional to the square of the predrive supply voltage.
According to another aspect of the invention, a predrive supply voltage compensation circuit comprises:
a predrive supply voltage; and
a bias current supply circuit configured to generate a predrive bias current that is proportional to the square of the predrive supply voltage and that is operational to cause a predrive to shift an output signal downward as the predrive supply voltage increases.
According to yet another aspect of the invention, a predrive supply voltage compensation circuit comprises:
a predrive supply voltage; and
means for generating a predrive bias current that is proportional to the square of the predrive supply voltage and capable of causing a predrive to shift an output signal downward in response to the predrive bias current as the predrive supply voltage increases.
According to still another aspect of the invention, a method of compensating predrive supply voltage changes comprises the steps of:
providing a predrive supply voltage and a means for generating a predrive bias current that is proportional to the square of the predrive supply voltage; and
causing a low voltage differential signaling predrive to shift a predrive output signal downward in response to the predrive bias current as the predrive supply voltage increases.